ユニティゲインバッファ段：U2(LT1363), U3(Lt1360), U4(LT1166)のM1とM2のゲート容量に対する
The LT1360 is stable with any capacitive load.
This is accomplished by sensing the load induced output pole
and adding compensation at the amplifier gain node.
As the capacitive load increases,
both the bandwidth and phase margin decrease
so there will be peaking in the frequency domain
and in the transient response
as shown in the typical performance curves.
The photo of the small signal response with 500pF load shows 60% peaking.
The large-signal response with a 10,000pF load shows
the output slew rate being limited to 5V/ms by the short-circuit current.
Coaxial cable can be driven directly,
but for best pulse fidelity a resistor of value equal to the characteristic
impedance of the cable (i.e., 75W) should be placed in series with the output.
The other end of the cable should be terminated with the same value resistor to ground.
The LT1360 circuit topology is a true voltage feedback amplifier
that has the slewing behavior of a current feedback amplifier.
The operation of the circuit can be understood by referring to the simplified schematic.
The inputs are buffered by complementary NPN and PNP emitter followers
which drive a 500W resistor.
The input voltage appears across the resistor generating currents
which are mirrored into the high impedance node.
Complementary followers form an output stage
which buffers the gain node from the load.
The bandwidth is set by the input resistor and the capacitance
on the high impedance node.
The slew rate is determined by the current available to charge the gain node capacitance.
This current is the differential input voltage divided by R1,
so the slew rate is proportional to the input.
Highest slew rates are therefore seen in the lowest gain configurations.
For example, a 10V output step in a gain of 10 has only a 1V input step,
whereas the same output step in unity gain has a 10 times greater input step.
The curve of Slew Rate vs Input Level illustrates this relationship.
The LT1360 is tested for slew rate
in a gain of –2 so higher slew rates can be expected in gains of 1
and –1, and lower slew rates in higher gain configurations.
The RC network across the output stage is bootstrapped
when the amplifier is driving a light or moderate load
and has no effect under normal operation.
When driving a capacitive load (or a low value resistive load)
the network is incompletely bootstrapped
and adds to the compensation at the high impedance node.
The added capacitance slows down the amplifier
which improves the phase margin
by moving the unity-gain frequency away from the pole formed
by the output impedance and the capacitive load.
The zero created by the RC combination adds phase
to ensure that even for very large load capacitances,
the total phase lag can never exceed 180 degrees (zero phase margin)
and the amplifier remains stable.