MOSFETの貫通電流対策

APPLICATION NOTE: AN003
Using Enhancement Mode GaN-on-Silicon Power FETs
を読んでいて気が付いたことをまとめておきます。

GaN MOSFETはトランスコンダクタンスが大きいため、
ゲートゾーベル、ゲート抵抗、ドライバのエミッタディジェネレーションの調整をきちんと行わないと、
最大入力での矩形波応で貫通電流が容易に発生します。

SPICEシミュレーションで容易に確認できますが、現象をきちんと理解するために、以下の記述を引用しておきます。

dv/dt Immunity

A high, positive-voltage slew rate (dv/dt) on the
drain of an off-state device can occur in both hard and
soft-switching applications,
and is characterized by a quick charging of the device’s capacitances as depicted in Figure 6.


During this dv/dt event, the drain-source capacitance (CDS) is charged.
Concurrently, the gate-drain (CGD) and gate-source (CGS)
capacitors in series also are charged.
If unaddressed, the charging current through the CGD capacitor will flow through and charge CGS beyond VTH and turn
the device on.
This event, sometimes called Miller turn-on and well known to MOSFET users, can be very dissipative.

To determine the dv/dt susceptibility of a power device,
a Miller charge ratio (QGD/QGS1),
as a function of drain-to-source voltage,
needs to be evaluated.
A Miller ratio of less than one will guarantee theoretical dv/dt immunity [1].
In Figure 7, the large reduction of Miller ratios in EPC’s latest generation eGaN FETs is shown,
reduced by at least a factor of twoand resulting in the entire product line falling below a value of 1 at half their rated voltage.

Also plotted, as triangular dots,
in Figure 7 are Miller ratios for current silicon MOSFETs which in general are much higher.

di/dt Immunity

A rising current through an off-state device,
as shown in Figure 8,

will induce a step voltage across the common-source inductance (CSI).
This positive voltage step will induce an opposing voltage across
CGS.


For a rising current, this causes the gate voltage to be driven to a negative value and,
with insufficient damping of the off-state gate loop LCR resonant
tank,
this initial negative voltage step across the gate could induce positive ringing
and cause an unintended turn-on and shoot-through as shown in
Figure 9.


It is possible to avoid this type of di/dt turn-on by sufficiently damping the gate turn-off loop,
although some level of undershoot may be preferred as described in the dv/dt immunity case above.
However, increasing the gate turn-off power loop damping through an increase in gate pulldown resistance would negatively impact dv/dt immunity.
Thus, adjusting gate resistance alone for devices with marginal Miller charge ratios may not be enough to avoid di/dt and/or dv/dt turn-on.
A better solution is to limit the size of the CSI through improved packaging and device layout.
This is accomplished by separating the gate and power loops to as close to the GaN device as possible,
and minimizing the internal source inductance of the GaN device, which will remain common to both loops.

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